In recent years significant progress is made in lowering the power consumption in medium- to high-speed (tens of MS/s to a few GS/s) and medium- to low-resolution (4 bit to 9 bit) A/D converters. Current state-of-the-art Figure of Merit (FoM) is 65 fJ. The FoM is determined as
  FoM  =      P                  2        ENOB            ·              F        sample            and represents the energy needed per conversion step. P denotes power in W, Fsample sample rate in 1/s and ENOB stands for the Effective Number of Bits. These efficiency improvements are primarily driven by mobile, wireless applications and sensor networks.
Flash architectures, as in WO2008/006751, are often chosen because they offer the largest speed. However, area and power depend exponentially on the resolution since the comparators are often the largest contributor to the overall power consumption. The bits are determined via a parallel search. On the other hand, a low-power SAR-based architecture is presented in patent application WO2007/088175.
Another possible approach to reduce the power consumption and increase the speed of a converter is by splitting the conversion process into two steps. A 1-bit folding front-end can for example be used in combination with a flash ADC as presented in patent document U.S. Pat. No. 6,369,726, reducing the number of comparators.
In patent document EP1079528-A1 a current-mode ADC is proposed that uses an asynchronous search algorithm in which each comparator in a set is triggered by its neighbour in a non-hierarchical way (i.e. all comparators have the same weight or importance), and a current is used to alter the input current. The architecture relies on current mode to realize low-voltage operation and hence to save on power.
In the paper “A current boosting full-flash ND converter” (Jungwook Yang et al., Proc. Int'l Symp. On Circuits and Systems, San Diego, vol. 2, 3 May 1992, pp. 609-612) the number of activated comparators in a flash converter is reduced by selecting a relevant set. The range finder circuit introduced by the authors are clocked synchronously (all at the same time) and based on their outputs only a part of the comparators of the flash converter are deactivated by reducing their biasing current and hence reducing power consumption.